Reducing power grid noise in a processor while minimizing performance loss
US9146772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Oct 18, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.