Programmable delay introducing circuit in self timed memory
US9147453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2014 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Nov 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.