Memory page buffer
US9147485B2 · kind B2 · utility
2Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Nov 2, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.