Integrated circuit fabrication
US9147608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2014 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Sep 15, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.