Patent · US Active

System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic

US9152511B2 · kind B2 · utility

4Cited by

6References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Michael Rohleder · Unterschleißheim, DE
Gary Hay · Whinstanes, AU
Stephan Mueller · Durham, US
Manfred Thanner · Neubiberg, DE

Key dates

Filing date	Jun 20, 2008
Grant date	Oct 6, 2015
Priority date	—
Expiry date	Jul 16, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/0411
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.