Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
US9152586B2 · kind B2 · utility
29Cited by
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4Claims
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Key dates
| Filing date | Oct 17, 2013 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Jan 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.