Method of fabricating high voltage device
US9153454B2 · kind B2 · utility
0Cited by
0References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2013 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Jul 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a high voltage device includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric below the conductive. The conductive layer and the dielectric layer are patterned by taking the patterned photoresist layer as a mask. Subsequently the patterned photoresist layer is shrunk. The conductive layer and the dielectric layer are then patterned by taking the shrunk photoresist layer as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.