FinFET gate with insulated vias and method of making same
US9153693B2 · kind B2 · utility
9Cited by
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17Claims
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Key dates
| Filing date | Jun 13, 2013 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Aug 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An intermediate semiconductor structure of a FinFET device in fabrication includes a substrate, a plurality of fin structures coupled to the substrate and a dummy gate disposed perpendicularly over the fin structures. A portion of the dummy gate is removed between the fin structures to create one or more vias and the one or more vias are filled with a dielectric. The dummy gate is then replaced with a metal gate formed around the dielectric-filled vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.