Patent · US Active

Packaging to reduce stress on microelectromechanical systems

US9156673B2 · kind B2 · utility

20Cited by

77References

9Claims

0Family size

Assignee

FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

Janusz Bryzek · Oakland, US
John Gardner Bloomsburgh · Oakland, US
Cenk Acar · Laguna Beach, US

Key dates

Filing date	Sep 18, 2011
Grant date	Oct 13, 2015
Priority date	—
Expiry date	Dec 13, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldMicro-structural and nano-technology
WIPO sectorChemistry

Abstract

One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.