Circuit design technique for DQS enable/disable calibration
US9158873B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2014 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Jun 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for calibrating a Data Strobe (DQS) enable/disable signal and for tracking the timing of the DQS enable/disable signal with respect to changes in voltage and temperature (VT) in order to improve the timing margin of the DQS enable/disable signal in programmable devices using Double Data Rate (DDR) memory. In an exemplary embodiment, the system includes a gating circuit, a sampling circuit, and a delay chain tracking circuit. The gating circuit receives a DQS enable signal and a input DQS signal, calibrates the DQS enable signal based on an amount of delay, and outputs the calibrated DQS signal. The sampling circuit provides the amount of delay to the gating circuit based on a sampling clock. The delay chain tracking circuit maintains the timing of the calibrated DQS enable signal over a plurality of clock cycles based on the sampling clock and a leveling clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.