Non-volatile memory with reduced sub-threshold leakage during program and erase operations
US9159425B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 25, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Nov 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.