Method for fabricating memory cells having split charge storage nodes

US9159568B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Chungho Lee · Sunnyvale, US
• Wei Zheng · Beijing, CN
• Chi Chang · Redwood City, US
• Unsoon Kim · San Jose, US
• Hiroyuki Kinoshita · San Jose, US

Key dates

• Filing date: Dec 15, 2006
• Grant date: Oct 13, 2015
• Expiry date: Dec 6, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/371

Abstract

Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.