Device and method for reducing contact resistance of a metal
US9159666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2014 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | May 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure for an integrated circuit includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes a TaN layer deposited on a side wall of the trench wherein the TaN layer has a greater concentration of nitrogen than tantalum, a Ta layer deposited on the TaN layer, and a Cu deposited on the Ta layer. The structure further includes a via integrated into the trench at bottom of the filled trench. In an embodiment, both the TaN layer and the Ta layer are formed with physical vapor deposition (PVD) wherein the TaN layer is formed with plasma sputtering a Ta target with an N2 flow at least 20 sccm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.