Data line arrangement and pillar arrangement in apparatuses

US9159736B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Luyen Vu · San Jose, US
• Mark A. Helm · Boise, US

Key dates

• Filing date: Feb 7, 2014
• Grant date: Oct 13, 2015
• Expiry date: Feb 17, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/83

Abstract

Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).