One-mask MTJ integration for STT MRAM
US9159910B2 · kind B2 · utility
8Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2009 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Apr 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.