Multiple heterogeneous NoC layers
US9160627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Jan 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/109
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the topology of different NoC layers and maps system traffic flows to various routes in various NoC layers that satisfies the latency requirements of the flows. The number of layers and their topology is dynamically allocated and optimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers and updating the topology of the NoC layers as they are mapped. In addition to allocating additional NoC layers and topologies to satisfy the latency requirements of the flows, the NoC layers and topologies may also be allocated to satisfy the bandwidth requirements of the flows or to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various flows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.