Analyzing data flow graph to detect data for copying from central register file to local register file used in different execution modes in reconfigurable processing array
US9164769B2 · kind B2 · utility
4Cited by
4References
17Claims
0Family size
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Key dates
| Filing date | Dec 8, 2010 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Sep 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.