Memory system with calibrated data communication
US9164933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2015 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Feb 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.