Method for providing a self-aligned pad protection in a semiconductor device

US9165821B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Michael Rogalli · Rottenburg am Neckar, DE
• Wolfgang Lehnert · Lintach, DE

Key dates

• Filing date: Dec 23, 2013
• Grant date: Oct 20, 2015
• Expiry date: Dec 23, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/94
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over the final metal layer and structuring the passivation layer and the final metal layer to form a patterned metal layer and a patterned passivation layer, wherein the patterned metal layer includes a pad region covered by the patterned passivation layer.