Process for producing at least one through-silicon via with improved heat dissipation, and corresponding three-dimensional integrated structure
US9165861B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | May 27, 2014 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | May 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on walls of the cavity, and at least partly on a first side outside the cavity. The process may further include at least partially filling the cavity with at least one phase-change material. Another aspect is directed to a three-dimensional integrated structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.