GaN transistor with improved bonding pad structure and method of fabricating the same
US9165896B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2014 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.