Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product
US9171117B2 · kind B2 · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2011 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Mar 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.