Parasitic extraction in an integrated circuit with multi-patterning requirements

US9171124B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. 2 LLC · US

Inventors

• Nathan C. Buck · Underhill, US
• Brian M. Dreibelbis · Underhill, US
• John P. Dubuque · Jericho, US
• Eric A. Foreman · Saint Albans, US
• Peter A. Habitz · South Burlington, US
• David J. Hathaway · Underhill Center, US
• Jeffrey G. Hemmett · South Burlington, US
• Natesan Venkateswaran · Hopewell Junction, US
• Chandramouli Visweswariah · Croton-on-Hudson, US
• Vladimir Zolotov · Putnam Valley, US

Key dates

• Filing date: Dec 23, 2013
• Grant date: Oct 27, 2015
• Expiry date: Dec 23, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/10
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form.