Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches

US9171735B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Sohan S. Mehta · Saratoga Springs, US
• Norman Chen · Poughkeepsie, US
• Yuyang Sun · Wappingers Falls, US
• Matthew T. Herrick · Austin, US
• Shyam Sundar Pal · Sherghati, IN
• Jeong Soo Kim · Daejeon, KR

Key dates

• Filing date: Feb 15, 2013
• Grant date: Oct 27, 2015
• Expiry date: Sep 12, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F7/0035
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.