Integrated circuit packaging system with coreless substrate and method of manufacture thereof
US9171739B1 · kind B1 · utility
9Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jun 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit packaging system, and a method of manufacture thereof, including: a patterned first conductive plating; a molding on the patterned first conductive plating; a through via through the molding; a second conductive plating on the molding and the through via; a protection layer partially covering the first conductive plating, the second conductive plating and the molding; a device on the first conductive plating; and an external connector being attached to the second conductive plating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.