Packaging substrate and fabrication method thereof
US9171741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2012 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.