Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process

US9171754B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Frank Koschinsky · Radebeul, DE
• Bernd Hintze · Rohrbach, DE
• Oliver Witnik · Radebeul, DE

Key dates

• Filing date: May 24, 2013
• Grant date: Oct 27, 2015
• Expiry date: Sep 7, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76828
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.