Cascode circuit
US9171837B2 · kind B2 · utility
3Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Dec 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.