Three-dimensional memory and method of forming the same
US9171862B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Mar 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a three-dimensional memory is provided. A stacked structure including semiconductor layers and insulating layers arranged alternately is formed on a substrate. The stacked structure is patterned to form a mesh structure having first strips extending in a first direction and second strips extending in a second direction. The first strips and the second strips intersect with each other. The mesh structure has first holes. A dielectric layer is formed in each first hole. At least a portion of the first strips of the mesh structure is removed to form second holes and bit line stacked structures separated from each other. A charge storage layer is formed on sidewall and bottom of each second hole. A gate pillar extending in a third direction is formed on each charge storage layer in the second hole. Word lines extending in the first direction are formed on the gate pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.