Method for fabricating semiconductor device
US9171915B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jul 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method for fabricating semiconductor device is disclosed. The method includes the steps of first providing a substrate, in which the substrate includes a SONOS region and a EEPROM region. Next, a first gate layer is formed in the SONOS region and the EEPROM region, the first gate layer is patterned by removing the first gate layer from the SONOS region and forming a floating gate pattern in the EEPROM region, an ONO layer is formed in the SONOS region and the EEPROM region, a second gate layer is formed on the ONO layer of the SONOS region and the EEPROM region, the second gate layer and the first gate layer are patterned to form a floating gate and a control gate in the EEPROM region, and the second gate layer is patterned to form a first gate in the SONOS region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.