Integrated antenna for RFIC package applications
US9172132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2015 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jan 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15321
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A chip package includes a set of layers including conductive planes connected by vias. A first portion has at least one antenna, antenna ground plane, and first grounded vias. A second portion has a conductive plane parallel to the ground plane that forms an interface for connecting to at least one integrated circuit device. A third portion between the first and the second portion has a vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit and a parallel-plate mode suppression mechanism. The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.