Two gate pitch FPGA memory cell
US9177634B1 · kind B1 · utility
1Cited by
4References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 4, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Feb 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node; a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the memory cell; and an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes; wherein the memory cell comprises a two gate pitch memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.