Methods for fabricating integrated circuits including barrier layers for interconnect structures

US9177858B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Xunyuan Zhang · Albany, US
• Tibor Bolom · Fishkill, US
• Kun Ho Ahn · Seoul, KR
• Bernd Hintze · Rohrbach, DE
• Frank Koschinsky · Radebeul, DE

Key dates

• Filing date: May 8, 2014
• Grant date: Nov 3, 2015
• Expiry date: May 8, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.