Circuit and method for controlling MRAM cell bias voltages
US9183912B2 · kind B2 · utility
8Cited by
21References
23Claims
0Family size
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Key dates
| Filing date | May 10, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Sep 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.