Stacked dual-chip packaging structure and preparation method thereof
US9184117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2012 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Apr 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.