Methods of forming FinFET devices in different regions of an integrated circuit product
US9184169B2 · kind B2 · utility
17Cited by
3References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 10, 2014 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one example, the method includes performing at least one process operation to form a first plurality of active fins and at least one sacrificial fin in a first area of a substrate while forming only a second plurality of active fins in a second area of said substrate, forming a fin removal masking layer that covers all of the active fins in both said first and second areas and exposes said at least one sacrificial fin in the first area, with the fin removal masking layer in position, performing at least one etching process to remove the at least one sacrificial fin in the first area and removing the fin removal masking layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.