Inventor · San Ramon, CA, US

Youngtag Woo

24Patents

8h-index

29Co-inventors

71Inventor score

Filing activity: Nov 16, 2004 → Sep 2, 2022

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8889561B2	Double sidewall image transfer process	Electricity	39	Active
US9711511B1	Vertical channel transistor-based semiconductor memory structure	Electricity	22	Active
US9406775B1	Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints	Electricity	21	Active
US9184169B2	Methods of forming FinFET devices in different regions of an integrated circuit product	Electricity	17	Active
US10236215B1	Methods of forming gate contact structures and cross-coupled contact structures for transistor devices	Electricity	13	Active
US9324722B1	Utilization of block-mask and cut-mask for forming metal routing in an IC device	Electricity	12	Active
US9105510B2	Double sidewall image transfer process	Electricity	12	Active
US9437481B2	Self-aligned double patterning process for two dimensional patterns	Electricity	8	Active
US9627389B1	Methods to form merged spacers for use in fin generation in IC devices	Electricity	6	Active
US10770388B2	Transistor with recessed cross couple for gate contact over active region integration	Electricity	6	Active
US9406616B2	Merged source/drain and gate contacts in SRAM bitcell	Electricity	5	Active
US9472464B1	Methods to utilize merged spacers for use in fin generation in tapered IC devices	Electricity	5	Active
US10651284B2	Methods of forming gate contact structures and cross-coupled contact structures for transistor devices	Electricity	4	Active
US12002869B2	Gate contact structures and cross-coupled contact structures for transistor devices	Electricity	2	Active
US9466604B2	Metal segments as landing pads and local interconnects in an IC device	Electricity	2	Active
US10204861B2	Structure with local contact for shorting a gate electrode to a source/drain region	Electricity	2	Active
US9268897B2	Method for increasing the robustness of a double patterning router used to manufacture integrated circuit devices	Emerging Cross-Sectional Technologies	2	Active
US10629701B1	Self-aligned gate cut method and multilayer gate-cut pillar structure	Electricity	2	Active
US7388262B2	Nitrogen implementation to minimize device variation	Electricity	1	Expired
US10109636B2	Active contact and gate contact interconnect for mitigating adjacent gate electrode shortages	Electricity	1	Active
US11469309B2	Gate contact structures and cross-coupled contact structures for transistor devices	Electricity	0	Active
US10490455B2	Gate contact structures and cross-coupled contact structures for transistor devices	Electricity	0	Active
US8962483B2	Interconnection designs using sidewall image transfer (SIT)	Electricity	0	Active
US10714591B2	Gate structure for a transistor device with a novel pillar structure positioned thereabove	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.