Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance
US9185023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Dec 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.