Performance based power management of a memory and a data storage system using the memory
US9189053B2 · kind B2 · utility
20Cited by
8References
17Claims
0Family size
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Key dates
| Filing date | Sep 23, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Sep 23, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power control circuitry for a data processor supplies a memory array with a supply voltage corresponding to a memory performance level. The performance levels include a full performance level and a power-saving performance level. Voltage sensing circuitry senses a voltage level of the memory array and outputs a power status signal. The power status signal is used to determine when the memory array is awake and can be accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.