Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9190390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2012 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Oct 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.