Fin field effect transistors having heteroepitaxial channels
US9190406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jan 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disposable gate structures are formed over semiconductor material portions, and source and drain regions can be formed in the semiconductor material portions. After formation of a planarization dielectric layer, one type of disposable gate structure can be removed selective to at least another type of disposable gate structure employing a patterned hard dielectric mask layer. After recessing a surface portion of a body portion, a heteroepitaxial channel portion is formed on the remaining physically exposed portion of the body portion by selective epitaxy of a semiconductor material different from the semiconductor material of the remaining body portion. A plurality of types of heteroepitaxial channel portions can be formed in different types of semiconductor devices. Replacement gate structures can be formed in the gate cavities to provide field effect transistors having different threshold voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.