Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby

US9190532B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Chunming Wang · Nanhu, CN
• Baowei Qiao · Chengdu, CN
• Zufa Zhang · Singapore, SG
• Yi Zhang · Austin, US
• Shiuh-Luen Wang · San Jose, US
• Wen-Juei Lu · Sunnyvale, US

Key dates

• Filing date: Aug 8, 2012
• Grant date: Nov 17, 2015
• Expiry date: Aug 8, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positio…