Latching level shifter and method of operation
US9191007B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jun 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latching level shifter coupled to a first power supply voltage is driven by a logic circuit coupled to a second power supply voltage. The latching level shifter is driven in a first mode to store a state based on an input signal received by the logic circuit, the first and second power supply voltages are set at first and second initial voltage levels. The latching level shifter is driven in a second mode subsequent to the first mode, the first power supply voltage is set to an intermediate voltage level. The latching level shifter is driven in a high voltage protection mode to produce an output voltage based on the state, the first power supply voltage is set to a final voltage level that is greater than a final voltage level of the second power supply voltage. The high voltage protection mode is subsequent to the second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.