Circuit and method for spin-torque MRAM bit line and source line voltage regulation
US9196342B2 · kind B2 · utility
7Cited by
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20Claims
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Key dates
| Filing date | Apr 1, 2015 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Apr 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.