Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate

US9196562B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dirk Siepe · Dortmund, DE
• Reinhold Bayerer · Warstein, DE

Key dates

• Filing date: Sep 7, 2011
• Grant date: Nov 24, 2015
• Expiry date: Oct 23, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/2076
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least 10 micrometers (μm), the thick metal layer comprises copper or a copper alloy, and the bonding wire or ribbon comprises copper or a copper-based material.