Semiconductor package with single sided substrate design and manufacturing methods thereof
US9196597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Aug 6, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.