Leakage reducing writeline charge protection circuit

US9196624B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Bradley Marc Davis · Fukushima, JP
• Mark Randolph · San Jose, US
• Sung-Yong Chung · Davis, US
• Hidehiko Shiraiwa · San Jose, US

Key dates

• Filing date: Jul 10, 2012
• Grant date: Nov 24, 2015
• Expiry date: Sep 1, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.