Error protection for a data bus
US9201727B2 · kind B2 · utility
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68References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Aug 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/356
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.