Techniques for detecting broken word lines in non-volatile memories
US9202593B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Sep 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for determining broken word lines in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. One set of techniques uses test program operation that alternates a standard staircase waveform with an elongated verify operation. This allows for a more accurate verify of under-programmed broken word lines relative to the standard verify operation. Another set of techniques looks at the ramp rate along the interconnect between the word line decoding circuitry and the main part of the word line. These techniques can also be used for determining defective select gate lines of an array with a NAND type structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.