Methods for forming semiconductor device packages
US9202714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2012 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Nov 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming semiconductor device packages include applying an underfill material over a semiconductor wafer including conductive elements such that an average thickness of the underfill material is at least about 80% of an average height of the conductive elements and each conductive element is covered by underfill material. Underfill material covering tips of conductive elements is removed. Other methods include positioning a stencil over a semiconductor wafer and applying an underfill material to a major surface of the semiconductor wafer through the stencil. Additional methods include aligning and associating conductive elements having a surface substantially free of underfill material with bond pads of a substrate, melting and flowing the underfill material, and heating the conductive elements and underfill material to melt tip portions of the conductive elements and cure the underfill material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.